Name: Ajay Kumar Manjanna
Date of Birth: 2nd Sept 1983
My Blog: http://sangfroidwa.blogspot.com/
Education:
Jamshedpur. India
Electronics Engineering [2002-2006]
CGPA: 8.62/10.00
Davangere, India
Grade 10 : 95.50%
Grade 12 : 93.33%
Expertise:
Programming Languages: C, Verilog HDL, HTML, XML, XSL
Platforms worked on: Texas Instruments' OMAP 3430 [3440], DSP TMS C55x/C64x, ARM9, ARM1176, ARM Cortex-A8
Protocols: Sonics OCP [Open Core Protocol], Philips I2C [Inter Integrated Circuit], Bosch's CAN [Controller Area Network], TI SPI [Serial Peripheral Interface], TI EMIF/SDRC/SMS [Memory controllers]
Tools: Agilent ADS, TI's Code Composer Studio [CCS], Novas's Verdi, Debussy, Mentor Graphics' Modelsim, Cadence's ncVerilog, ORCAD's Schematic capture & PCB Layout
Probing Instruments: Agilent Technologies' Logical Analyzer [Traditional & USB], I2C Bus Analyzer, 1GHz Oscilloscopes
Academic Projects:
>> Electrostatic Reflection Microscope [Group Size: 2]
A better way imaging at nanoscales, Texas Instruments.
A novel method of imaging was proposed which bypasses the major problems being faced by the present imaging technologies used by tolls like Scanning Tunneling Microscope (STM), Atomic Force Microscope (AFM), etc. This project was submitted as an entree for TI Design Contest'04 This project was awarded thefirst Prize by Texas Instruments in ‘TI Developer’s Conference-04’.
>>Pharma SFA (Sales Force Automation) [Group Size: 2]
A mobile application for Blackberry mobile using J2ME.
This project was pursued as a part of summer internship in SASKEN Communications, Bangalore. Objective of the project was to build a prototype of the Pharma-Sales Force Automation software client on the BlackBerry handset using J2ME. The Client prototype for the Pharma-Sales Force Automation shall be residing in the BlackBerry handset, the communication mechanisms with the server, and the workflow were designed.
>>Adaptive Equalizer [Group Size: 2]
An adaptive filter designed using Matlab.
This project was pursued as UG final year project. The objective of the project was to design a adaptive filter using MATLAB tool to render the noiseless signal at the receiver end. Also a Noise-Antinoise filter was designed, where the filter produces antinoise and thus canceling the noise in the transmitted signal. The project was graded excellent and was adjudged the best in Electronics Engineering Dept that year [2006].
Industrial Projects:
>> OMAPV1035 (ECOSTO) SOC Pre-Silicon Validation [TI Application Processor]
OMAPV1035 chip is a GGE (GSM GPRS EDGE) single-chip modem integrating the digital baseband (DBB) and an Edge Digital Radio Processor (DRPe) as well as multimedia applications thereby maximizing the system integration for cost reduction. It is based on the enhanced OMAP™ 2.3 Architecture integrated on a 65nm process. It has ARM926J as master and C55X DSP as slave cores
Contributions:
1. Responsible for Zebu based Pre-Silicon validation [Execution of SDRC Subsystem & DSP subsystem in OMAPV1035].
2. Silicon Validation plan for OMAP SDRC.System flow,
3 Stress and Performance validation.
4. Helped my colleagues in debugging the issues.
>> OMAPV2320 (N3G2) SOC Pre-Silicon and Post Silicon Validation [TI Base band Processor]
The OMAPV2320 device is a GGE/WCDMA/HSDPA Modem and multimedia application processor based on the enhanced OMAP™ 2.3 Architecture integrated on a 65nm process. The architecture is designed to provide Video, Audio and graphics processing sufficient to support: streaming video, electronic games, video conferencing, and still picture capture and display in 3G wireless terminals. It has ARM1172 as master and C55X DSP as slave core.
Contribution:
1. Responsible for Zebu based Pre-Silicon validation [Execution of SDRC Subsystem & DSP subsystem in OMAPV2320]
2. Silicon Validation plans for SDRC.
3. System flow, Stress and Performance validation.
4. Validation of SDRC, SMS and part of DSP blocks.
5. Was able to validate and debug the issues independently.
6. Trained my colleagues for the CCS usage and Test Case flow.
7. Was awarded the Team of the Quarter at the corporate level for the effort put into validation and completing the assigned task well within the deadline.
>> OMAP3430 SOC Post-Silicon Validation [TI Application Processor]
OMAP3430 device is a high performance multimedia application device based on the enhanced OMAPTM2.3 architecture integrated on 65 nm. The device is targeted for low power video, audio and graphics applications. It has ARM1176 and C64X DSP as master and slave cores respectively.
Contribution:
1. Validation of SDRC and SMS: Test case development for SDRC and SMS modules targeted for post-silicon environment.
2. Stress (Multi-Initiator Single-Target, Multi-Initiator Multi-Target) validation.
3. Automated the process using scripts
4. Scripted a script to check the adherence to guidelines by a test case.
5. Was given spot award inrecognition of my performance.
>> Corazon [DA225] AV&V (Application Verification and Validation) [TI low power Application Processor]
Corazón is a member of TI's C5500 fixed-point DSP product family that is designed for ultra low power applications. Its C55x DSP Subsystem achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation.
Contribution:
1. Developed test cases to validate modules such as Real time Clock, Memory interface, idle control logic, SPI and UART.
2. Implemented the regression suite for all the test cases of all the modules.
3. Debugged and fixed some of the hardware issues on the board and on the design.
4. Helped the team in understanding the board and IC architecture and some debugging tools.
5. Was given spot award inrecognition of my performance.
>> SHIVA AV&V (Application Verification and Validation)
SHIVA is OMAP3430 architecture based application processor targetted for GPS application and handheld devices. I'm presently working on this project
Contribution:
1. Developed testcase to test an application scenario.
2. Developed testcases to measure Memory controller, HECC [High End CAN Controller] & ARM Cortex A-8 throughputs in the SOC.
3. Ramped up 3 of the team members on the architecture, AVV flow and the usage of debug tools
Papers Presented:
>> Electrostatic Reflection microscope
An innovative paper presented in TI Developers’ Conference organized by Texas Instruments, Bangalore
>> Optimization of MEMS switches using Genetic Algorithm
An innovative paper presented at KSHITIJ-06, Technical Fest at IIT Kharagpur
>> Nanotechnology
A review paper presented in a National conference on “Emerging trends in Nanotechnology & innovations in Manufacturing and Designing”, organized at NIT Rourkela. This paper was published in the national journal released by NT Rourkela.
>> Integration of CRM with ERP
An innovative paper presented in TECHNICA-06, Technical Fest organized by Dept of Metallurgy, NIT Jamshedpur.
Awards and Honours:
> Recipient of First Prize in TI design Contest-04 (National level), conducted by Texas Instruments, Bangalore, India.
> Recipient of State merit award and gold medal for securing 7th rank in the state and 1st in the school.
> Recepient of Team of the Quarter award for the performance at work.
> Recipient of spot award from customer [Texas Instruments] twice for showing excellence at work.
Books that have laid my foundation:
1. Digital Design and principles by John F. Wakerly
2. ARM System Developer's Guide by Andrew N. Sloss, Symes and Wright
3. ASIC by Michael John Sebastian Smith
4. Microelectronic Circuits by Sedra & Smith
5. Design of Analog CMOS Integrated Circuits by Behzad Razavi
6. Digital Integrated Circuits - A Design perspective by Jan M. Rabaey
